The present invention relates to a method for fabricating a semiconductor device, and more particularly, to a method for fabricating a semiconductor device including a transistor.
As a semiconductor device becomes highly integrated, a channel length of a cell transistor in a semiconductor device such as a dynamic random access memory (DRAM) is significantly reduced to cause a short channel effect. Hence, a transistor having a three-dimensional channel structure such as a recess gate is adopted in order to increase an effective channel length of the transistor.
The recess gate is formed by etching an active region of a substrate by a predetermined depth and forming the gate inside the recess.
In a semiconductor device such as the DRAM, a landing plug contact (LPC) process is performed after a gate formation process.
The LPC process will now be briefly described. A nitride layer for spacers is formed over a substrate including gates (including recess gates) in order to protect the gates during subsequent self aligned contact (SAC) etching process.
An interlayer insulation layer covering the gates is formed over the nitride layer. A SAC etching process is performed on the interlayer insulation layer and the nitride layer to form an opening exposing an active region of the substrate between the gates.
The opening is filled with a conductive material to form a conductive plug, which will be connected to a bit line or a storage node. In this way, the LPC process is completed.
Such a landing plug contact must be self-aligned with the gates and be able to secure an open margin. However, due to the high integration density of the semiconductor device, a space between the gates is reduced an thus it is difficult to meet the demands at the same time.
More specifically, in the SAC etching process for forming the landing plug contact, the reduction in the space between the gates makes it difficult to completely remove the nitride layer on the bottom of the opening, thus causing a “not open fail” of the landing plug contact.
In order to prevent the “not open fail” of the landing plug contact, an over etching process may be performed by increasing an etching time during the SAC etching process for forming a landing plug contact. In this case, however, a hard mask formed over the uppermost of the gate may be excessively lost causing the SAC fail between the landing plug contact and the gate. In addition, a method for reducing a critical dimension (CD) may be used. However, this method may cause a gate leaning.
Since these limitations occurring during the landing plug contact formation process and greatly reduce the yield of the semiconductor device, there is need for technologies that can prevent the limitations.